{
  "endpoint": "/hardware/memory.json",
  "status": "beta",
  "as_of": "2026-05-10",
  "schema_version": "0.1.0-draft",
  "license": "CC-BY-4.0",
  "description": "Curated directory of memory technologies relevant to AI accelerators and agent compute. Numbers are JEDEC / vendor published peaks per stack/module/channel.",
  "schema": {
    "id": "stable slug identifier",
    "name": "common product / standard name",
    "category": "hbm | gddr | ddr | lpddr | sram | emerging",
    "generation": "spec version",
    "capacity": "typical capacity per stack/module/channel (GB)",
    "bandwidth_gb_s": "peak bandwidth per stack/module/channel",
    "data_rate_gt_s": "data rate per pin",
    "bus_width_bits": "interface width",
    "stack_height": "DRAM dies per stack (HBM only)",
    "vendors": "primary suppliers",
    "typical_use": "where this is deployed",
    "status": "production | sampling | announced | legacy",
    "source": "primary spec URL"
  },
  "count": 20,
  "items": [
    {
      "id": "hbm4-16hi-48gb",
      "name": "HBM4 16-Hi",
      "category": "hbm",
      "generation": "HBM4",
      "capacity": 48,
      "bandwidth_gb_s": 2000,
      "data_rate_gt_s": 6.4,
      "bus_width_bits": 2048,
      "stack_height": 16,
      "vendors": ["SK Hynix", "Samsung", "Micron"],
      "typical_use": "NVIDIA Rubin, AMD MI400-class accelerators",
      "status": "sampling",
      "source": "https://www.tomshardware.com/tech-industry/semiconductors/hbm-roadmaps-for-micron-samsung-and-sk-hynix-to-hbm4-and-beyond"
    },
    {
      "id": "hbm4-12hi-36gb",
      "name": "HBM4 12-Hi",
      "category": "hbm",
      "generation": "HBM4",
      "capacity": 36,
      "bandwidth_gb_s": 2000,
      "data_rate_gt_s": 8,
      "bus_width_bits": 2048,
      "stack_height": 12,
      "vendors": ["Micron", "SK Hynix"],
      "typical_use": "Next-gen training accelerators",
      "status": "sampling",
      "source": "https://www.blocksandfiles.com/hci/2026/01/28/high-bandwidth-memory-v4-supply-takes-shape/4090314"
    },
    {
      "id": "hbm3e-12hi-36gb",
      "name": "HBM3E 12-Hi",
      "category": "hbm",
      "generation": "HBM3e",
      "capacity": 36,
      "bandwidth_gb_s": 1280,
      "data_rate_gt_s": 9.8,
      "bus_width_bits": 1024,
      "stack_height": 12,
      "vendors": ["SK Hynix", "Micron", "Samsung"],
      "typical_use": "NVIDIA B200/GB200/GB300, AMD MI325X/MI355X",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "id": "hbm3e-8hi-24gb",
      "name": "HBM3E 8-Hi",
      "category": "hbm",
      "generation": "HBM3e",
      "capacity": 24,
      "bandwidth_gb_s": 1200,
      "data_rate_gt_s": 9.2,
      "bus_width_bits": 1024,
      "stack_height": 8,
      "vendors": ["SK Hynix", "Micron", "Samsung"],
      "typical_use": "NVIDIA H200, early B200 SKUs",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "id": "hbm3-16gb",
      "name": "HBM3",
      "category": "hbm",
      "generation": "HBM3",
      "capacity": 16,
      "bandwidth_gb_s": 819,
      "data_rate_gt_s": 6.4,
      "bus_width_bits": 1024,
      "stack_height": 8,
      "vendors": ["SK Hynix", "Samsung", "Micron"],
      "typical_use": "NVIDIA H100, AMD MI300X, Google TPU v5p",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "id": "hbm2e-16gb",
      "name": "HBM2E",
      "category": "hbm",
      "generation": "HBM2e",
      "capacity": 16,
      "bandwidth_gb_s": 460,
      "data_rate_gt_s": 3.6,
      "bus_width_bits": 1024,
      "stack_height": 8,
      "vendors": ["SK Hynix", "Samsung", "Micron"],
      "typical_use": "NVIDIA A100 80GB, AMD MI250X, Intel Gaudi 3",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "id": "hbm2",
      "name": "HBM2",
      "category": "hbm",
      "generation": "HBM2",
      "capacity": 8,
      "bandwidth_gb_s": 256,
      "data_rate_gt_s": 2,
      "bus_width_bits": 1024,
      "stack_height": 8,
      "vendors": ["SK Hynix", "Samsung"],
      "typical_use": "NVIDIA V100, A100 40GB, Google TPU v4",
      "status": "legacy",
      "source": "https://en.wikipedia.org/wiki/High_Bandwidth_Memory"
    },
    {
      "id": "gddr7-32gbps",
      "name": "GDDR7 (32 Gbps)",
      "category": "gddr",
      "generation": "GDDR7",
      "capacity": 2,
      "bandwidth_gb_s": 128,
      "data_rate_gt_s": 32,
      "bus_width_bits": 32,
      "stack_height": null,
      "vendors": ["Samsung", "Micron", "SK Hynix"],
      "typical_use": "NVIDIA RTX 5090, next-gen consumer GPUs",
      "status": "production",
      "source": "https://semiconductor.samsung.com/dram/gddr/gddr7/"
    },
    {
      "id": "gddr6x-24gbps",
      "name": "GDDR6X (24 Gbps)",
      "category": "gddr",
      "generation": "GDDR6X",
      "capacity": 2,
      "bandwidth_gb_s": 96,
      "data_rate_gt_s": 24,
      "bus_width_bits": 32,
      "stack_height": null,
      "vendors": ["Micron"],
      "typical_use": "NVIDIA RTX 4090, RTX 40 series flagships",
      "status": "production",
      "source": "https://www.micron.com/products/graphics-memory/gddr6x"
    },
    {
      "id": "gddr6-20gbps",
      "name": "GDDR6 (20 Gbps)",
      "category": "gddr",
      "generation": "GDDR6",
      "capacity": 2,
      "bandwidth_gb_s": 80,
      "data_rate_gt_s": 20,
      "bus_width_bits": 32,
      "stack_height": null,
      "vendors": ["Samsung", "Micron", "SK Hynix"],
      "typical_use": "NVIDIA L40S, RTX 6000 Ada, AMD RX 7900 XTX",
      "status": "production",
      "source": "https://www.samsung.com/semiconductor/dram/gddr6/"
    },
    {
      "id": "ddr5-6400",
      "name": "DDR5-6400 DIMM",
      "category": "ddr",
      "generation": "DDR5",
      "capacity": 64,
      "bandwidth_gb_s": 51.2,
      "data_rate_gt_s": 6.4,
      "bus_width_bits": 64,
      "stack_height": null,
      "vendors": ["Samsung", "SK Hynix", "Micron"],
      "typical_use": "Host CPU memory for AI servers, CXL pools",
      "status": "production",
      "source": "https://www.jedec.org/standards-documents/docs/jesd79-5"
    },
    {
      "id": "ddr5-4800",
      "name": "DDR5-4800 DIMM",
      "category": "ddr",
      "generation": "DDR5",
      "capacity": 32,
      "bandwidth_gb_s": 38.4,
      "data_rate_gt_s": 4.8,
      "bus_width_bits": 64,
      "stack_height": null,
      "vendors": ["Samsung", "SK Hynix", "Micron"],
      "typical_use": "Baseline server DRAM for current-gen CPUs",
      "status": "production",
      "source": "https://www.jedec.org/standards-documents/docs/jesd79-5"
    },
    {
      "id": "lpddr5x-8533",
      "name": "LPDDR5X-8533",
      "category": "lpddr",
      "generation": "LPDDR5X",
      "capacity": 16,
      "bandwidth_gb_s": 68,
      "data_rate_gt_s": 8.533,
      "bus_width_bits": 64,
      "stack_height": null,
      "vendors": ["Samsung", "SK Hynix", "Micron"],
      "typical_use": "NVIDIA Grace, Apple M-series, edge SoCs",
      "status": "production",
      "source": "https://www.jedec.org/standards-documents/docs/jesd209-5b"
    },
    {
      "id": "lpddr5-6400",
      "name": "LPDDR5-6400",
      "category": "lpddr",
      "generation": "LPDDR5",
      "capacity": 16,
      "bandwidth_gb_s": 51.2,
      "data_rate_gt_s": 6.4,
      "bus_width_bits": 64,
      "stack_height": null,
      "vendors": ["Samsung", "SK Hynix", "Micron"],
      "typical_use": "Jetson Orin, Meta MTIA, mobile/edge AI",
      "status": "production",
      "source": "https://www.jedec.org/standards-documents/docs/jesd209-5"
    },
    {
      "id": "sram-on-die-l2",
      "name": "On-die SRAM (L2)",
      "category": "sram",
      "generation": "process-dependent (3-7nm typical)",
      "capacity": 0.05,
      "bandwidth_gb_s": 5000,
      "data_rate_gt_s": null,
      "bus_width_bits": null,
      "stack_height": null,
      "vendors": ["TSMC", "Samsung Foundry", "Intel Foundry"],
      "typical_use": "Per-cluster cache in GPUs/CPUs; sub-ns latency",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/Static_random-access_memory"
    },
    {
      "id": "sram-llc",
      "name": "On-die LLC SRAM",
      "category": "sram",
      "generation": "process-dependent",
      "capacity": 0.128,
      "bandwidth_gb_s": 10000,
      "data_rate_gt_s": null,
      "bus_width_bits": null,
      "stack_height": null,
      "vendors": ["TSMC", "Samsung Foundry"],
      "typical_use": "Last-level cache; 24-128 MB in high-end accelerators",
      "status": "production",
      "source": "https://en.wikipedia.org/wiki/CPU_cache"
    },
    {
      "id": "infinity-cache",
      "name": "AMD Infinity Cache (GPU LLC)",
      "category": "sram",
      "generation": "RDNA3 / CDNA3",
      "capacity": 0.256,
      "bandwidth_gb_s": 5300,
      "data_rate_gt_s": null,
      "bus_width_bits": null,
      "stack_height": null,
      "vendors": ["AMD"],
      "typical_use": "AMD Radeon and Instinct GPUs (up to 256 MB)",
      "status": "production",
      "source": "https://www.amd.com/en/technologies/infinity-cache.html"
    },
    {
      "id": "wafer-scale-sram",
      "name": "Wafer-scale SRAM (Cerebras WSE-3)",
      "category": "sram",
      "generation": "5nm",
      "capacity": 44,
      "bandwidth_gb_s": 21000000,
      "data_rate_gt_s": null,
      "bus_width_bits": null,
      "stack_height": null,
      "vendors": ["Cerebras"],
      "typical_use": "WSE-3 wafer-scale inference/training",
      "status": "production",
      "source": "https://www.cerebras.ai/chip"
    },
    {
      "id": "cxl-2-memory-pool",
      "name": "CXL 2.0 Memory Pool (DDR5-backed)",
      "category": "emerging",
      "generation": "CXL 2.0/3.0",
      "capacity": 512,
      "bandwidth_gb_s": 64,
      "data_rate_gt_s": 32,
      "bus_width_bits": 16,
      "stack_height": null,
      "vendors": ["Samsung", "SK Hynix", "Micron", "Astera Labs"],
      "typical_use": "Disaggregated memory pools for inference clusters",
      "status": "production",
      "source": "https://www.computeexpresslink.org/"
    },
    {
      "id": "mram-stt",
      "name": "STT-MRAM",
      "category": "emerging",
      "generation": "Embedded MRAM",
      "capacity": 0.064,
      "bandwidth_gb_s": null,
      "data_rate_gt_s": null,
      "bus_width_bits": null,
      "stack_height": null,
      "vendors": ["Samsung", "TSMC", "Everspin"],
      "typical_use": "Non-volatile embedded cache; emerging in edge AI SoCs",
      "status": "sampling",
      "source": "https://en.wikipedia.org/wiki/Magnetoresistive_RAM"
    }
  ]
}